The present invention relates generally to the field of iterative error detection and correction algorithms. More particularly, the present invention relates to a system and method for real time optimization of iterative error detection and correction (EDAC) algorithms.
Wireless communication channels are used to transmit data wirelessly from a transmitting module to a receiving module. However, during wireless transmission of data, the data that is being transmitted may become corrupted. Corruption creates errors in the data such that the data that was transmitted is not the same as the data that is received. Corruption is more likely to occur wherever the communication channel has a low signal to noise ratio, as often occurs with wireless communication.
Various algorithms have been developed to attempt to detect and correct errors that have been introduced during the transmittal of data. These algorithms are called error detection and correction (EDAC) algorithms. Error detection and correction algorithms increase the accuracy of data transmitted, but the increase in accuracy is often associated with a decrease in throughput (the amount of data that passes through the channel within any defined period). The decrease in throughput is generally caused by the processing time during error detection and correction and the addition of EDAC information to fixed size data packets, reducing the amount of “real” data in each packet.
Error detection and correction algorithms include a collection of methods to detect errors in transmitted or stored data and to correct them. The error detection and correction may be performed using any of a variety of algorithms. The simplest form of error detection is a single added parity bit or a cyclic redundancy check. However, using multiple parity bits can enable an algorithm to not only detect that an error has occurred, but also which bits have been inverted, and should therefore be re-inverted to restore the original data. In general, the more extra bits are added, the greater the chance that multiple errors will be detectable and correctable.
More sophisticated error detection and control algorithms are often implemented in a turbo code encoding and decoding system. An encoder is implemented in the transmitter and a decoder is implemented in the receiver. Turbo codes are a class of error-control coding systems that offer near optimal performance, i.e. throughput while requiring only moderate complexity. Turbo codes are generally decoded using an iterative decoding algorithm wherein a packet is iteratively decoded to increasingly reduce errors. Up to a point of diminishing returns, the greater the number of iterations allowed, the more an input packet can be corrupted and still be decoded correctly.
While error detection and correction is being performed on a first packet, additional packets may be received by the receiver. These packets are placed in a queue. While the first packet is being processed, the packets remaining in the queue are not processed or analyzed, causing a reduction in throughput (the total number of packets processed by the decoder within a given time). The number of iterations a packet is processed by the decoder can greatly affect the throughput of the wireless channel. However, the reduction in throughput is balanced against the accuracy of the error detection and correction. In other words, increasing the number of iterations increases the amount of time packets stay in the queue but also increases error detection and correction accuracy.
To prevent excessive reduction in throughput, limits have been placed on the number of iterations to be performed by the decoder. The limits are determined by balancing throughput against error detection and correction. Previously, the limits have been static values.
What is needed is a system and method for optimizing an error detection and correction algorithm to provide increased error detection and control accuracy while maintaining a high throughput rate. What is further need is such a system and method configured to increase error detection and correction accuracy when the decoder queue is close to empty and increase throughput when the decoder queue is close to full.
It would be desirable to provide a system and/or method that provides one or more of these or other advantageous features. Other features and advantages will be made apparent from the present specification. The teachings disclosed extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the aforementioned needs.